Lot Acceptance Testing (LAT)

We have noticed that some of our customers are referencing MIL-PRF-19500 Appendix G “Discrete Semiconductor Die/Chip Lot Acceptance” Table XII for die evaluation.

The stated purpose of Appendix G is to, “establish minimum standards for screening and qualification of JANHC and JANKC unencapsulated discrete semiconductor devices (die/chips)”

While this document is for wafer manufacturers that are on the QPL to qualify dice from the same QPL line, we see that customer source control drawings are starting to reference Table XII of this appendix for lot acceptance purposes pertaining to transistor and diode chips.

Although this table is similar to Table C-II of 38534, there are differences. Stabilization, temperature cycling and die shear have been added to the Class H requirements with an option for HTRB and Burn-in when specified on the “performance specification sheet”.

The minimum electrical requirement of Table C-II of 38534 is “static” tests at . +25C, max rated operating temperature . minimum operating temperature. Table XII of 19500 appendix G has electrical requirements called out by subgroups of Group A from the appropriate 19500 slash sheet. These are subgroups 2, 3 and 4. Subgroup 2 is 25C static, subgroup 3 is normally static @ high temperature and subgroup 4 is normally functional at 25C.

Sample size for both methods is 10 pieces with zero rejects. All methods of inspection for discrete devices in the MIL-PRF-19500 table are from MIL-STD-750, which is for discrete devices. All methods in 38534 are from MIL-STD-883, except the MIL-STD-750 options for Visual and SEM. MIL-STD-883 addresses itself mainly to Integrated Circuits.

In conclusion; whatever die element evaluation is referenced, SemiDice will respond to the customers requirements.