Micron Offers Superior Quality and a Broad Range of Wafer Level Products through Semi Dice Bare die is complex: processing, handling, and storing unpackaged silicon require experience and expertise. Few distributors are equipped to cope with the complexities of bare die. This is why Micron Technology, Inc., recently signed a distributor agreement with Semi Dice. Through this agreement, Semi Dice will supply the North American market with Micron’s memory and imager bare die products.
“This agreement enables Micron and Semi Dice to support our mutual customers with bare die products and a wide range of value-added programs,” said Steve King, Micron’s Wafer-Level Business Development Manager. “With Semi Dice’s strong reputation for commitment to quality, service, and customer relationships, and their experience in handling bare die semiconductors, we believe they are the right organization to further expand our bare die distribution network.”
Quality and Reliability
Wafer-level products reduce board area in packaging technologies such as systems-in-a-package (SIPs) and multichip packages (MCPs). With reduced trace lengths between devices, bare die-based solutions also enable higher-frequency operation as processor and bus speeds increase. These benefits can come at a cost, however. The poorest performing die in the stack determines the quality of an MCP, so the burden falls on memory manufacturers to deliver bare die products that maintain reliability and quality levels similar to fully tested and burned-in packaged devices.
Wafer-level quality requires that the silicon is fully functional when assembled in the final product. While it can be measured in many ways, quality is generally represented as the number of defective parts per the number of good parts, or defective parts per million (DPM).
Wafer-level reliability is defined as how long the device continues to meet a customer’s expectations (versus quality, which is measured one time at initial test only). Reliability is typically expressed in failures in time, or as a FIT rate. A FIT is a failure per billion device hours. If a group of devices has a FIT rate of 100, the customer could expect an estimated 100 failures per billion device hours. While this coverage is more than adequate for most bare die applications, the emergence of SiP and MCP applications requires new levels of quality and reliability test coverage.
Comprehensive functional coverage at wafer test provides high-quality die, while proprietary wafer-level stress is used to reduce infant mortalities. In addition, data from Micron’s AMBYX™ burn-in system provides detailed failure information, which is correlated to abundant wafer parametric and functional data. This enables Micron to predict failure rates and ensure the highest standards for known good die (KGD) applications. Micron understands design requirements and is able to apply the proper amount of screening at the wafer or discrete die level. Two fully developed test programs help them achieve an optimum balance between reliability and cost-effectiveness.
Standard wafer-level known good die testing (KGD-C1) provides the most cost-effective test coverage for bare die products. The quality of the bare die is verified by testing for speed, functionality, and margin fails. The testing includes elevated-temperature probing with functional and parametric tests, and high-voltage functional stress tests. Wafer-level parts are subjected to highly accelerated DC voltage stress. Performed at high temperatures, typically 90°C-105°C, the DC voltage stress test can detect most memory array defects by applying static bias to the main terminals of the array, the row lines, the digit lines, and the cell plate. The test patterns, timing margins, and test sequences are determined by product maturity and yields. This coverage is more than adequate for most bare die applications.
Parts that meet all the requirements of KGD-C1 testing may undergo additional testing at the C2 level. The KGD-C2 program begins with the standard quality tests, including die stress, but then extends to testing die for full functionality of published AC/DC and speed specifications. A hot die sort (HDSRT) at the upper temperature limit ensures that devices conform to the full AC and DC parameters of their respective data sheets. Depending on the product, ambient die sort (ADSRT) or cold die sort (CDSRT) testing may be done to screen parts for full conformity to specifications at the lower temperature limit. This enhanced wafer-level testing ensures that Micron’s bare die products meet the industry’s highest specifications.
In a growing number of designs where speed and space are critical, bare die is indispensable: high-density modules in graphics applications, DSL chipsets in digital TVs, multichip module hybrids or SiPs in wireless applications, and combinations of devices with SRAM and DRAM in network processing technologies. This extensive array of memory and imagers is available to designers in die form. Its superior quality and reliability is ensured by Micron’s two levels of KGD testing. These fully tested die products are then backed by world-class technical support-support that only a manufacturer with 25 years of experience can provide.
This support extends to both established and emerging markets, as the need for small form factor solutions continues to grow because of their considerable design flexibility. “Semi Dice is well positioned to address the growth in small form factor solutions with bare die products. Our ability to support these requirements with Micron Technology components, the industry leader in memory products, allows us to support a rapidly growing market segment” said Daniel Cormack, CEO of Semi Dice.
Broad Product Offering
Micron’s extensive portfolio of memory and CMOS image sensor products in wafer form include SDRAM, DDR SDRAM, DDR2 SDRAM, Mobile SDR and DDR SDRAM, CellularRAM™ memory, Boot Block Flash, Q-Flash® Memory, and CMOS image sensors. Semi Dice offers these products in either die or wafer form, along with value-added test services to meet customers’ specific design requirements. A variety of configurations and packaging options are also available through Semi Dice. For technical information on Micron’s bare die product line, see http://www.micron.com/products/baredie/ and sign in to the bare die secure site.
© 2005 Micron Technology, Inc. All rights reserved. Micron and the Micron logo are trademarks of Micron Technology, Inc. All information discussed herein is provided “AS IS” and without warranties of any kind.